Manufacturing Science and Technology Group’s three sessions this year are on two government-industry efforts and a third repeat session on machine learning (ML) for process control. The first government-industry effort to be highlighted are those authorized and funded by the CHIPS and Science Act of 2022. Government, Industry, and Academic speakers will present early results of industry direct grants for manufacturing as well as grants for joint R&D and for Workforce Development–especially through STEM education. The second session will highlight what is needed as semiconductor manufacturing reaches its miniaturization limits in two dimensions (2D), it has moved to 2.5D and 3D which greatly increases the number and importance of metrology steps as well as the importance of decreasing process variability. ML although initially considered to be a subset of Artificial Intelligence (AI) and used to train AI, it is now a separate discipline focused more on probability theory and statistics that is becoming widely used worldwide especially in microelectronics’ to reduce process variability. In our ML session, speakers from a wide range of microelectronics manufacturing and research organizations will discuss improved or even autonomous process control. To date, commercial applications of ML for process control mainly have been for ex-situ parameter development. But for autonomous or other in-situ (real-time) uses of ML, energy use could become both an economic and environmental concern. Recently, however, experts have identified best practices that can lower in-situ ML energy use by orders of magnitude: For example, selecting efficient ML model architectures while advancing ML quality, such as sparse models versus dense modes, can reduce computation by factors of ~5–10 and using processors optimized for ML training such as TPUs or recent GPUs (e.g., V100or A100), versus general-purpose processors, can improve performance/Watt by factors of 2–5. For the afternoon session, we note semiconductor manufacturing trends that demand significantly advanced characterization and modelling: As device size shrinks toward the size of the probe being used, structures become more difficult to image accurately; Measuring structures or films that are not accessible from the surface or are hidden under pre-existing layers is a major challenge; In 3D, the complexity of structures increases geometrically with 3D device architectures and accessing some 3D features with non-destructive techniques can be difficult. The third session highlights the need for and progress made to date on a new Department of Energy-led effort to develop an RD&D Roadmap to ensure that microelectronics energy efficiency gets back on the path of doubling energy efficiency every two years–i.e. through “Energy Efficiency Scaling”. This microelectronics Energy Efficiency Scaling for 2 decades (EES2) roadmap involves working groups across the stack (Device and Materials, Circuits and Architectures, Software and Algorithms, Advanced Packaging and Heterogeneous integration) as well as Enabling Working Groups for Power and Control electronics, Metrology and Benchmarking and Manufacturing Energy Efficiency and Sustainability (7 WG total). The EES2 Roadmap is projected to be complete by Fall 2023 and hopefully will be rolled out (or at least a sneak preview) at this AVS Session.
MS+AP+AS+TF-ThA: Machine Learning for Microelectronics Manufacturing Process Control
- Kanad Basu, University of Texas at Dallas, “Machine Learning-based Atomic Layer Deposition”
- Keren Kanarik, LAM Research, “Human-Machine Collaboration for Improving Semiconductor Process Development”
MS-FrM: Microelectronics R&D for Life-Cycle Energy Efficiency
- Paul Fischer, Intel Corp., “Materials, Devices, and Packaging Opportunities Towards a Super Energy Efficient Future”
- Jay Lewis, Microsoft, “Energy Efficiency Scaling for 2 Decades–an update”
- Godwin Maben, Synopsys, Inc, “Improving Asic Energy Efficiency from Systems to Silicon”
- Shashank Misra, Sandia National Laboratories, “Atomic Precision Advanced Manufacturing for Tunnel Field Effect Transistors”
- Sadasivan Shankar, SLAC National Accelerator Laboratory, “Energy Efficient Scaling in Microelectronics: Enabling a New Era in Computing for a Sustainable Future”
MS-ThP: Manufacturing Science and Technology Poster Session